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Электронный компонент: PEEL22CV10ASI-7

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High Speed/Low Power
- Speeds ranging from 7ns to 25ns
- Power as low as 30mA at 25MHz
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Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
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Development/Programmer Support
- Third party software and programmers
- Anachip PLACE Development Software
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Architectural Flexibility
- 132 product term X 44 input AND array
- Up to 22 inputs and 10 outputs
- Up to 12 configurations per macrocell
- Synchronous preset, asynchronous clear
- Independent output enables
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
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Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Enhanced Architecture fits more logic
than ordinary PLDs
Features
The PEELTM22CV10A is a Programmable Electrically Eras-
able Logic (PEELTM) device providing an attractive alterna-
tive to ordinary PLDs. The PEELTM22CV10A offers the
performance, flexibility, ease of design and production
practicality needed by logic designers today. The
PEELTM22CV10A is available in 24-pin DIP, SOIC, TSSOP
and 28-pin PLCC packages (see Figure 1), with speeds
ranging from 7ns to 25ns and with power consumption as
low as 30mA. EE-reprogrammability provides the conve-
nience of instant reprogramming for development and a
reusable production inventory, minimizing the impact of
programming changes or errors. EE-reprogrammability
also improves factory testability, thus ensuring the highest
quality possible. The PEELTM22CV10A is JEDEC file com-
patible with standard 22V10 PLDs. Eight additional configu-
rations per macrocell (a total of 12) are also available by
using the "+" software/programming option (i.e., 22CV10A+
& 22CV10A++). The additional macrocell configurations
allow more logic to be put into every design. Programming
and development support for the PEELTM22CV10A are pro-
vided by popular third-party programmers and develop-
ment software. Anachip also offers free PLACE
development software.
General Description
DIP
*Optional extra ground pin for
-7/I-7 speed grade.
PLCC
1
2
3
4
5
6
7
8
I/CLK
I
I
I
I
I
I
I
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
23
22
21
20
19
18
17
9
10
I
I
I/O
I/O
16
15
11
12
I
GND
I/O
I
14
13
TSSOP
SOIC
Figure 1. Pin Configuration
Figure 2. Block Diagram
CMOS Programmable Electrically Erasable Logic Device
PEELTM 22CV10A-7/-10/-15/-25
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131
124
130
111
98
83
82
66
49
33
20
21
2
0
9
10
34
48
65
121
110
97
I
I
I
I
I
I
I
I/CLK
I
I
I
MACRO
CELL
ASYNCHRONOUS CLEAR
(TO ALL MACROCELLS)
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
MACRO
CELL
SYNCHRONOUS PRESET
(TO ALL MACROCELLS)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
Figure 3. PEELTM22CV10A Logic Array Diagram
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Function Description
The PEELTM22CV10A implements logic functions as sum-
of-products expressions in a programmable-AND/ fixed-OR
logic array. User-defined functions are created by program-
ming the connections of input signals into the array. User-
configurable output structures in the form of I/O macrocells
further increase logic flexibility.
Architecture Overview
The PEELTM22CV10A architecture is illustrated in the block
diagram of Figure 2. Twelve dedicated inputs and 10 I/Os
provide up to 22 inputs and 10 outputs for creation of logic
functions. At the core of the device is a programmable elec-
trically-erasable AND array which drives a fixed OR array.
With this structure, the PEELTM22CV10A can implement up
to 10 sum-of-products logic expressions.
Associated with each of the 10 OR functions is an I/O mac-
rocell which can be independently programmed to one of 4
different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic
functions with either active-high or active-low polarity.
AND/OR Logic Array
The programmable AND array of the PEELTM22CV10A
(shown in Figure 3) is formed by input lines intersecting
product terms. The input lines and product terms are used
as follows:
44 Input Lines:
24 input lines carry the true and complement
of the signals applied to the 12 input pins
20 additional lines carry the true and complement
values of feedback or input signals from
the 10 I/Os
132 product terms:
120 product terms (arranged in 2 groups of 8,
10, 12, 14 and 16) used to form logical sums
10 output enable terms (one for each I/O)
1 global synchronous present term
1 global asynchronous clear term
At each input-line/product-term intersection there is an
EEPROM memory cell which determines whether or not
there is a logical connection at that intersection. Each prod-
uct term is essentially a 44-input AND gate. A product term
which is connected to both the true and complement of an
input signal will always be FALSE, and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a "don't care" state exists and
that term will always be TRUE. When programming the
PEELTM22CV10A, the device programmer first performs a
bulk erase to remove the previous pattern. The erase cycle
opens every logical connection in the array. The device is
then configured to perform the user-defined function by
programming selected connections in the AND array. (Note
that PEELTM device programmers automatically program
the connections on unused product terms so that they will
have no effect on the output function.)
Variable Product Term Distribution
The PEELTM22CV10A provides 120 product terms to drive
the 10 OR functions. These product terms are distributed
among the outputs in groups of 8, 10, 12, 14 and 16 to form
logical sums (see Figure 3). This distribution allows opti-
mum use of device re-sources.
Programmable I/O Macrocell
The output macrocell provides complete control over the
architecture of each output. The ability to configure each
output independently permits users to tailor the configura-
tion of the PEELTM22CV10A to the precise requirements of
their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 4, consists of a D-
type flip-flop and two signal-select multiplexers. The config-
uration of each macrocell is determined by the two
EEPROM bits controlling these multiplexers (refer to Table
1). These bits determine output polarity and output type
(registered or non-registered). Equivalent circuits for the
four macro-cell configurations are illustrated in Figure 5.
Output Type
The signal from the OR array can be fed directly to the out-
put pin (combinatorial function) or latched in the D-type flip-
flop (registered function). The D-type flip-flop latches data
on the rising edge of the clock and is controlled by the glo-
bal preset and clear terms. When the synchronous preset
term is satisfied, the Q output of the register will be set
HIGH at the next rising edge of the clock input. Satisfying
the asynchronous clear term will set Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously,
the clear will override the preset.
Output Polarity
Each macrocell can be configured to implement active-high
or active-low logic. Programmable polarity eliminates the
need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable
output enable product term. When the logical conditions
programmed on the output enable term are satisfied, the
output signal is propagated to the I/O pin. Otherwise, the
output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
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enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
When configuring an I/O macrocell to implement a regis-
tered function (configurations 1 and 2 in Figure 5), the Q
output of the flip-flop drives the feedback term. When con-
figuring an I/O macrocell to implement a combinatorial
function (configurations 3 and 4 in Figure 5), the feedback
signal is taken from the I/O pin. In this case, the pin can be
used as a dedicated input or a bi-directional I/O. (Refer
also to Table 1.)
Additional Macro Cell Configurations
Besides the standard four-configuration macrocell shown in
Figure 5, each PEELTM22CV10A provides an additional
eight configurations that can be used to increase design
flexibility. The configurations are the same as provided by
the PEELTM18CV8 and PEELTM22CV10AZ. However, to
maintain JEDEC file compatibility with standard 22V10
PLDs the additional configurations can only be utilized by
specifying the PEELTM22CV10A+ and PEEL22CV10A++
for logic assembly and programming. To reference these
additional configurations please refer to the specifications
at the end of this data sheet.
Design Security
The PEELTM22CV10A provides a special EEPROM secu-
rity bit that prevents unauthorized reading or copying of
designs programmed into the device. The security bit is set
by the PLD programmer, either at the conclusion of the pro-
gramming cycle or as a separate step after the device has
been programmed. Once the security bit is set, it is impos-
sible to verify (read) or program the PEELTM until the entire
device has first been erased with the bulk-erase function.
Signature Word
The signature word feature allows a 24-bit code to be pro-
grammed into the PEELTM22CV10A if the
PEELTM22CV10A+ software option is used. Also, the sig-
nature word feature allows a 64-bit code to be programmed
into the PEELTM22CV10A if the PEELTM22CV10A++ soft-
ware option is used. The code can be read back even after
the security bit has been set. The signature word can be
used to identify the pattern programmed into the device or
to record the design revision, etc.
Figure 4. Block Diagram of the PEELTM 22CV10A I/O Macrocell.
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Figure 5. Four Configurations of the PEELTM22CV10A I/O Macrocell
Table 1. PEELTM 22CV10A Macrocell Configuration Bits
Configuration
Input/Feedback Select
Output Select
#
A B
1
0
0
Register Feedback
Register
Active Low
2
1
0
Active High
3
0
1
Bi-Directional I/O
Combinatorial
Active Low
4
1
1
Active High
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Additional Macrocell Configurations
Besides the standard four-configuration macrocells, each
PEELTM22CV10A provides an additional eight configura-
tions (twelve total) that can be used to increase design flex-
ibility
(see Figure 6 and Table 2). For logic assembly of all twelve
configurations, specify PEELTM22CV10A+ and
PEEL22CV10A++.
Configuration
Input/Feedback Select
Output Select
#
A B C D
1
1 1 1 1
Bi-Directional I/O
Register
Active Low
2
0 1 1 1
Active High
3
1 0 1 1
Combinatorial
Active Low
4
0 0 1 1
Active High
5
1 1 1 0
Combinatorial Feedback
Register
Active Low
6
0 1 1 0
Active High
7
1 0 1 0
Combinatorial
Active Low
8
0 0 1 0
Active High
9
1 1 0 0
Register Feedback
Register
Active Low
10
1 0 0 0
Active High
11
1 0 0 0
Combinatorial
Active Low
12
0 0 0 0
Active High
Figure 6. Twelve Configurations of the PEELTM22CV10A+ and PEEL22CV10A++ I/O Macrocell
Table 2. PEELTM 22CV10A+ & A++ Macrocell Configuration Bits
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Table 6. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Ratings
Unit
V
CC
Supply Voltage
Relative to Ground
-0.5 to + 7.0
V
V
I
, V
O
Voltage Applied to Any Pin
2
Relative to Ground
1
-0.5 to V
CC
+ 0.6
V
I
O
Output Current
Per pin (I
OL
, I
OH
)
25
mA
T
ST
Storage Temperature
-65 to + 150
C
T
LT
Lead Temperature
Soldering 10 seconds
+300
C
Table 7. Operating Ranges
Symbol
Parameter
Conditions
Min
Max
Unit
V
CC
Supply Voltage
Commercial
4.75
5.25
V
Industrial
4.5
5.5
T
A
Ambient Temperature
Commercial
0
+70
C
Industrial
-40
+85
T
R
Clock Rise Time
See Note 3
20
ns
T
F
Clock Fall Time
See Note 3
20
ns
T
RVCC
V
CC
Rise Time
See Note 3
250
ms
Table 8. D.C. Electrical Characteristics over the recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
V
OH
Output HIGH Voltage
V
CC
= Min, I
OH
= -4.0mA
2.4
V
V
OHC
Output HIGH Voltage - CMOS
13
V
CC
= Min, I
OH
= -10A
V
CC
- 0.3
V
V
OL
Output LOW Voltage - TTL
V
CC
= Min, I
OL
= 16mA
0.5
V
V
OLC
Output LOW Voltage - CMOS
13
V
CC
= Min, I
OH
= -10A
0.15
V
V
IH
Input HIGH Level
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Level
-0.3
0.8
V
I
IL
Input Leakage Current
V
CC
= Max, V
IN
= GND
V
IN
V
CC
10
A
I
OZ
Output Leakage Current
I/O = High-Z, GND
V
O
V
CC
10
A
ICC
10
V
CC
Current
(See CR-1 for typical I
CC
)
V
IN
= 0V or 3V
f = 25MHz
All outputs disabled
4
-7/I-7
90/100
mA
-10/I-10
90/100
-15/I-15
135/145
-25/I-25
30/40
C
IN
7
Input Capacitance
T
A
= 25C, V
CC
= 5.0V
@ f = 1 MHz
6
pF
C
OUT
7
Output Capacitance
12
pF
This device has been designed and tested for the recommended
operating conditions. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings may cause per-
manent damage.
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Table 9. A.C. Electrical Characteristics
Symbol
Parameter
-7 / I-7
-10 / I-10
-15 / I-15
-25 / I-25
Unit
Min
Max
Min
Max
Min
Max
Min
Max
t
PD
Input
5
to non-registered output
7.5
10
15
25
ns
t
OE
Input
5
to output enable
6
7.5
10
15
25
ns
t
OD
Input5 to output disable
6
7.5
10
15
25
ns
t
CO1
Clock to Output
5.5
6
8
15
ns
t
CO2
Clock to comb. output delay via
internal registered feedback
10
12
17
35
ns
t
CF
Clock to Feedback
3.5
4
5
9
ns
t
SC
Input
5
or Feedback Setup to Clock
3
5
8
15
ns
t
HC
Input
5
Hold After Clock
0
0
0
0
ns
t
CL
, t
CH
Clock Low Time, Click High Time
8
3
4
6
13
ns
t
CP
Min Clock Period Ext (t
SC
+ t
CO1
)
8.5
11
18
30
ns
f
MAX1
Internal Feedback (1
tSC
+ t
CF
)
12
142
111
76.9
41.6
MHz
f
MAX2
External Feedback (1/t
CP
)
12
117
90.9
62.5
33.3
MHz
f
MAX3
No Feedback (1/t
CL
+ t
CH
)
12
166
125
83.3
38.4
MHz
t
AW
Asynchronous Reset Pulse Width
7.5
10
15
25
ns
t
AP
Input
5
to Asynchronous Reset
7.5
10
15
25
ns
t
AR
Asynch. Reset recovery time
7.5
10
15
25
ns
t
RESET
Power-on Reset Time for
registers in Clear State
5
5
5
5
s
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes
1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for
periods less than 20ns.
2. V
I
and V
O
are not specified for program/verify operation.
3. Test points for Clock and V
CC
in t
R
, t
F
are referenced at 10% and 90%
levels.
4. I/O pins are 0V and 3V.
5. "Input" refers to an Input pin signal.
6. t
OE
is measured from input transition to V
REF
0.1V, t
OD
is measured
from input transition to V
OH
-0.1V or V
OL
+0.1V; V
REF
=V
L
see test loads
in Section 5 of the Data Book.
7. Capacitances are tested on a sample basis.
8. Test conditions assume: signal transition times of 3ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
9. Test one output at a time for a duration of less than 1sec.
10. ICC for a typical application: This parameter is tested with the device
programmed as an 8-bit Counter.
11. PEELTM Device test loads are specified in Section 6 of this Data Book.
12. Parameters are not 100% tested. Specifications are based on initial
characterization and are tested after any design or process modifica-
tion which may affect operational frequency.
13. Available only for 22CV10A -15/I-15/-25/I-25 grades.
Switching Waveforms
Over the Operating Range
8,11
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Table 6. Ordering Information
Part Number
Speed
Temperature
Package
PEEL22CV10AP-7
7.5ns
C
P24
PEEL22CV10API-7
I
PEEL 22CV10AJ-7
7.5ns
C
J28
PEEL 22CV10AJI-7
I
PEEL 22CV10AS-7
7.5ns
C
S24
PEEL 22CV10ASI-7
I
PEEL 22CV10AT-7
7.5ns
C
T24
PEEL 22CV10ATI-7
I
PEEL 22CV10AP-10
10ns
C
P24
PEEL 22CV10API-10
I
PEEL 22CV10AJ-10
10ns
C
J28
PEEL 22CV10AJI-10
I
PEEL 22CV10AS-10
10ns
C
S24
PEEL 22CV10ASI-10
I
PEEL 22CV10AT-10
10ns
C
T24
PEEL 22CV10ATI-10
I
PEEL 22CV10AP-15
15ns
C
P24
PEEL 22CV10API-15
I
PEEL 22CV10AJ-15
15ns
C
J28
PEEL 22CV10AJI-15
I
PEEL 22CV10AS-15
15ns
C
S24
PEEL 22CV10ASI-15
I
PEEL 22CV10AT-15
15ns
C
T24
PEEL 22CV10ATI-15
I
PEEL 22CV10AP-25
25ns
C
P24
PEEL 22CV10API-25
I
PEEL 22CV10AT-25
25ns
C
T24
PEEL 22CV10ATI-25
I
PEEL 22CV10AJ-25
25ns
C
J28
PEEL 22CV10AJI-25
I
PEEL 22CV10AS-25
25ns
C
S24
PEEL 22CV10ASI-25
I
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Part Number
Device
PEELTM 22CV10A PI-25
Package
P = Plastic 300mil DIP
J = Plastic (J) Leaded Chip Carrier (PLCC)
S = SOIC
T = TSSOP
Temperature Range and Power Options
(Blank) = Commercial 0 to 70C
I = Industrial -40 to +85C
Speed
-7 = 7.5ns tpd
-10 = 10ns tpd
-15 = 15ns tpd
-25 = 25ns tpd
Suffix